The present disclosure relates to a semiconductor device, and more particularly relates to a technique for implementing a semiconductor integrated circuit by 3D process technologies.
In recent years, the progress of LSI (large scale integrated circuits) microfabrication processes has enabled highly dense integration of great many components in a chip. As a result, the performance of semiconductor integrated circuits has been improved significantly in terms of miniaturization, multi-functionality, and high response speed, among other things. As the microfabrication processes progress, various problems such as an increase in leakage current involving heat generation of transistors, and wiring delay become more and more serious. Consequently, it has become increasingly difficult to achieve further miniaturization on a two-dimensional plane of a chip. Thus, 3D implementation technologies for stacking a plurality of chips vertically one upon the other have been suggested to overcome those problems.
As such a semiconductor device, disclosed is a chip-on-chip (CoC) type semiconductor device in which two chips are bonded to each other by facedown bonding method with their centers of gravity shifted from each other (see, e.g., Japanese Unexamined Patent Publication No. 2005-183934). Such shifted arrangement of two chips allows for connecting an edge portion of the lower chip to an external device via bonding wires, even if the upper chip is larger in size than the lower chip.